Multi-mode clock (MMC) circuit networks refer to circuit networks with multiple clocks for different modes of operation. In general, the modes of operation are mutually exclusive, and thus, all the clocks in a MMC circuit network cannot be active simultaneously. An example of a MMC circuit network is shown in FIG. 1. The circuit network 100 has two modes, namely, functional mode and test mode. In functional mode, the clock signal, func_clk, is active. Likewise, in test mode, the clock signal, test_clk, is active. The sequential elements (e.g., ff1 and ff2) in the circuit network 100 are clocked by a multiplexer (MUX) 110. The MUX 110 selects one of the inputs, func_clk and test_clk, in response to the mode signal, test_enable.
During timing analysis on the circuit network, if the value of the mode signal is not specified, one conventional timing analysis tool analyzes paths from func_clk to test_clk, and vice versa. For example, a setup violation may be reported at the D-input terminal of ff2 (i.e., ff2/D) due to a data signal launched by func_clk and a clock signal captured by test_clk. The corresponding clock path has func_clk going through ff1/CP, ff1/Q, and ff2/D sequentially (i.e., func_clk=>ff1/CP=>ff1/Q=>ff2/D) and the clock signal, test_clk going through ff2/CP (i.e., test_clk=>ff2/CP). Since func_clk and test_clk are mutually exclusive, the above violation is impossible in the corresponding circuit network in practice. Hence, the above clock path is referred to as a false path.
False paths that arise from mutually exclusive clocks are problematic in timing analysis and optimization flows because they may cause invalid alarms or error reports. One conventional approach to timing optimization is to perform multiple timing analysis runs during optimization for all possible modes of operation. A typical optimization tool cannot determine if the worst-case timing has been met unless the analysis has been done for all possible modes. Thus, this approach is unsatisfactory because of the increase in flow complexity.
A second conventional approach performs one timing analysis run during optimization while assuming all possible modes of operation. However, since some clock signals are mutually exclusive, there are one or more false paths when all modes of operation are assumed to be possible. To handle the false paths, circuit designers have to manually identify the false paths. Since this manual identification process is tedious and error-prone, the second approach is also undesirable.